1. Field of the Invention
The present invention is generally directed to the field of semiconductor manufacturing, and, more particularly, to a transistor having a gate stack comprised of a metal, and a method of making same.
2. Description of the Related Art
There is a constant drive within the semiconductor industry to increase the operating speed of integrated circuit devices, e.g., microprocessors, memory devices, and the like. This drive is fueled by consumer demands for computers and electronic devices that operate at increasingly greater speeds. This demand for increased speed has resulted in a continual reduction in the size of semiconductor devices, e.g., transistors. That is, many components of a typical field effect transistor (FET), e.g., channel length, junction depths, gate insulation thickness, and the like, are reduced. For example, all other things being equal, the smaller the channel length of the transistor, the faster the transistor will operate. Thus, there is a constant drive to reduce the size, or scale, of the components of a typical transistor to increase the overall speed of the transistor, as well as integrated circuit devices incorporating such transistors.
In attempting to improve the performance of integrated circuit devices, one area of potential improvement involves using a metal as a gate electrode material. Many modem integrated circuit devices are comprised of transistors having polysilicon gate electrodes. However, due to the decreased resistance of a metal as compared to polysilicon, metal is an attractive option for the gate electrodes of transistors to increase the overall operating speed of the transistor device.
A transistor 10 having an illustrative gate stack 11 comprised of a metal is shown in FIGS. 1A-1B. As shown therein, the transistor 10 is formed in an active region 14 of a semiconducting substrate 12 as defined by isolation structures 16. The transistor 10 is comprised of the gate stack 11, sidewall spacers 20 and a plurality of source/drain regions 18. With further reference to FIG. 1A, the gate stack 11 is comprised of a gate insulation layer 22, a layer of titanium nitride 24, and a layer of metal 26. The gate insulation layer 22 is comprised of silicon dioxide, and it has a thickness of approximately 1-5 nm. The titanium nitride layer 24 has a thickness of approximately 15 nm, and the metal layer 26 is comprised of tungsten and it has a thickness of approximately 50 nm. The gate insulation layer 22 is typically formed by a thermal oxidation process. The titanium nitride layer 24 and the metal layer 26 are typically formed by a physical vapor deposition process. During fabrication, additional process layers may be formed above the metal layer 26. For example, a silicon nitride anti-reflective coating (ARC) layer (not shown) may be formed above the metal layer 26, and a silicon nitride cap layer (not shown) may be formed above the ARC layer.
Although the gate stack 11 structure depicted in FIGS. 1A-1B does exhibit lower resistance due to the presence of the metal layers 24, 26, the work-function of the resulting transistor is not as desirable as that of a polysilicon gate. In general, the work-function is a primary parameter that determines the threshold voltage between the gate electrode material and the doping level in the substrate. In a sense, the work-function can be thought of as a kind of electrical compatibility. The lower the work-function, the lower the threshold voltage, the lower the power required to run the circuit, etc. All other things being equal, it would be desirable to reduce the work-function of the gate stack 11. Moreover, in the configuration depicted in FIGS. 1A-1B, the presence of the titanium nitride layer 24 tends to create undesirable mid-gap states in the gate insulating layer 22. Such mid-gap states tend to cause increased leakage currents in the completed transistor.
The present invention is directed to a method that may solve, or at least reduce, some or all of the aforementioned problems.
The present invention is generally directed to a transistor having a gate stack comprised of a metal, and a method of making same. In one illustrative embodiment, the transistor is comprised of a gate stack comprised of a gate insulation layer positioned above a semiconducting substrate, a layer of silicon positioned above the gate insulation layer, a layer of adhesion material positioned above the layer of silicon, a layer of metal positioned above the layer of adhesion material, and a plurality of source/drain regions formed in the substrate adjacent the gate stack. In further illustrative embodiments, the gate stack is comprised of a gate insulation layer, the layer of silicon is implanted with dopant atoms, the adhesion layer is comprised of titanium nitride, and the metal layer is comprised of tungsten.